Sciweavers

1992 search results - page 62 / 399
» Memory modeling for system synthesis
Sort
View
DAC
2003
ACM
16 years 25 days ago
Automated synthesis of efficient binary decoders for retargetable software toolkits
A binary decoder is a common component of software development tools such as instruction set simulators, disassemblers and debuggers. The efficiency of the decoder can have a sign...
Wei Qin, Sharad Malik
ETS
2007
IEEE
91views Hardware» more  ETS 2007»
15 years 6 months ago
PPM Reduction on Embedded Memories in System on Chip
This paper summarizes advanced test patterns designed to target dynamic and time-related faults caused by new defect mechanisms in deep-submicron memory technologies. Such tests a...
Said Hamdioui, Zaid Al-Ars, Javier Jiménez,...
3DIC
2009
IEEE
169views Hardware» more  3DIC 2009»
15 years 5 months ago
3-D memory organization and performance analysis for multi-processor network-on-chip architecture
Several forms of processor memory organizations have been in use to optimally access off-chip memory systems mainly the Hard disk drives (HDD). Recent trends show that the solid s...
Awet Yemane Weldezion, Zhonghai Lu, Roshan Weerase...
CDC
2008
IEEE
103views Control Systems» more  CDC 2008»
15 years 6 months ago
Symbolic models for nonlinear control systems affected by disturbances
Abstract— Symbolic models are abstract descriptions of continuous systems in which symbols represent aggregates of continuous states. In the last few years there has been a growi...
Giordano Pola, Paulo Tabuada
ICC
2007
IEEE
15 years 6 months ago
On the Impact of Ignoring Markovian Channel Memory on the Analysis of Wireless Systems
– Recent wireless measurement studies have revealed the presence of high-order memory in wireless bit-error channels. However, most wireless studies continue to employ the memory...
Syed A. Khayam, Hayder Radha