40 search results - page 1 / 8 » Memory-Aware Application Mapping on Coarse-Grained Reconfigu... |
68
Voted
HIPEAC
2010
Springer
15 years 26 days ago
2010
Springer
88
Voted
ASAP
2005
IEEE
15 years 4 months ago
2005
IEEE
It is widely known that parallel operation execution in multiprocessor systems generates a respective increase in memory accesses. Since the memory and bus subsystems provide a li...
85
Voted
IPPS
2006
IEEE
15 years 4 months ago
2006
IEEE
In this paper, we present performance results from mapping five real-world DSP applications on an embedded system-on-chip that incorporates coarse-grain reconfigurable logic with ...
95
Voted
ESTIMEDIA
2007
Springer
15 years 2 months ago
2007
Springer
Due to the increasing demands on efficiency, performance and flexibility reconfigurable computational architectures are very promising candidates in embedded systems design. Recent...
83
Voted
FPL
2006
Springer
15 years 2 months ago
2006
Springer
We present a heavily parametrized tool suite that allows the modeling and exploration of heterogeneous, coarse-grained, heavily pipelined reconfigurable architectures. Our tools p...