39 search results - page 4 / 8 » Memory-aware NoC Exploration and Design |
91
Voted
DATE
2009
IEEE
15 years 5 months ago
2009
IEEE
- In this paper, we present a design methodology for automatic platform generation of future heterogeneous systems where communication happens via the Network-onChip (NoC) approach...
ICCD
2006
IEEE
15 years 8 months ago
2006
IEEE
—This paper presents a system-level Network-on-Chip modeling framework that integrates transaction-level model and analytical wire model for design space exploration. It enables ...
CORR
2006
Springer
14 years 11 months ago
2006
Springer
We introduce a new approach to take into account the memory architecture and the memory mapping in the High- Level Synthesis of Real-Time embedded systems. We formalize the memory...
77
Voted
ICCD
2006
IEEE
15 years 8 months ago
2006
IEEE
— As the geometries of the transistors reach the physical limits of operation, one of the main design challenges of Systems-on-Chips (SoCs) will be to provide dynamic (run-time) ...
MICRO
2010
IEEE
14 years 9 months ago
2010
IEEE
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...