Sciweavers

39 search results - page 5 / 8
» Memory-aware NoC Exploration and Design
Sort
View
63
Voted
NOCS
2009
IEEE
15 years 4 months ago
Exploring concentration and channel slicing in on-chip network router
Sharing on-chip network resources efficiently is critical in the design of a cost-efficient network on-chip (NoC). Concentration has been proposed for on-chip networks but the t...
Prabhat Kumar, Yan Pan, John Kim, Gokhan Memik, Al...
DSN
2006
IEEE
15 years 3 months ago
Exploring Fault-Tolerant Network-on-Chip Architectures
The advent of deep sub-micron technology has exacerbated reliability issues in on-chip interconnects. In particular, single event upsets, such as soft errors, and hard faults are ...
Dongkook Park, Chrysostomos Nicopoulos, Jongman Ki...
DATE
2005
IEEE
116views Hardware» more  DATE 2005»
15 years 3 months ago
A Complete Network-On-Chip Emulation Framework
Current Systems-On-Chip (SoC) execute applications that demand extensive parallel processing. Networks-OnChip (NoC) provide a structured way of realizing interconnections on silic...
Nicolas Genko, David Atienza, Giovanni De Micheli,...
ISCAS
2005
IEEE
146views Hardware» more  ISCAS 2005»
15 years 3 months ago
A novel approach for network on chip emulation
— Current Systems-On-Chip execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon...
Nicolas Genko, David Atienza, Giovanni De Micheli,...
SC
2009
ACM
15 years 4 months ago
Allocator implementations for network-on-chip routers
The present contribution explores the design space for virtual channel (VC) and switch allocators in network-on-chip (NoC) routers. Based on detailed RTL-level implementations, we...
Daniel U. Becker, William J. Dally