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» Memory-aware NoC Exploration and Design
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ISCA
2007
IEEE
110views Hardware» more  ISCA 2007»
15 years 3 months ago
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
Much like multi-storey buildings in densely packed metropolises, three-dimensional (3D) chip structures are envisioned as a viable solution to skyrocketing transistor densities an...
Jongman Kim, Chrysostomos Nicopoulos, Dongkook Par...
ISVLSI
2006
IEEE
129views VLSI» more  ISVLSI 2006»
15 years 3 months ago
Connection-oriented Multicasting in Wormhole-switched Networks on Chip
Network-on-Chip (NoC) proposes networks to replace buses as a scalable global communication interconnect for future SoC designs. However, a bus is very efficient in broadcasting....
Zhonghai Lu, Bei Yin, Axel Jantsch
SBCCI
2005
ACM
98views VLSI» more  SBCCI 2005»
15 years 3 months ago
Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation
This work addresses the problem of application mapping in networks-on-chip (NoCs). It explores the importance of characterizing network traffic to effectively predict NoC energy c...
José Carlos S. Palma, César A. M. Ma...
CODES
2005
IEEE
15 years 3 months ago
Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs
To ensure low power consumption while maintaining flexibility and performance, future Systems-on-Chip (SoC) will combine several types of processor cores and data memory units of...
Anthony Leroy, Paul Marchal, Adelina Shickova, Fra...