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HIPEAC
2007
Springer
15 years 3 months ago
Performance/Energy Optimization of DSP Transforms on the XScale Processor
The XScale processor family provides user-controllable independent configuration of CPU, bus, and memory frequencies. This feature introduces another handle for the code optimizat...
Paolo D'Alberto, Markus Püschel, Franz Franch...
CODES
2003
IEEE
15 years 3 months ago
Design space minimization with timing and code size optimization for embedded DSP
One of the most challenging problems in high-level synthesis is how to quickly explore a wide range of design options to achieve high-quality designs. This paper presents an Integ...
Qingfeng Zhuge, Zili Shao, Bin Xiao, Edwin Hsing-M...
DAC
1995
ACM
15 years 1 months ago
A Transformation-Based Approach for Storage Optimization
High-level synthesis (HLS) has been successfully targeted towards the digital signal processing (DSP) domain. Both application-speci c integrated circuits (ASICs) and application-...
Wei-Kai Cheng, Youn-Long Lin
ISCAS
2002
IEEE
124views Hardware» more  ISCAS 2002»
15 years 2 months ago
Performance optimization of multiple memory architectures for DSP
Multiple memory module architecture offers higher performance by providing potentially doubled memory bandwidth. Two key problems in gaining high performance in this kind of archi...
Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha
SCOPES
2005
Springer
15 years 3 months ago
Software Synthesis from the Dataflow Interchange Format
Specification, validation, and synthesis are important aspects of embedded systems design. The use of dataflow-based design environments for these purposes is becoming increasingl...
Chia-Jui Hsu, Shuvra S. Bhattacharyya