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» Memory-constrained aggregate computation over data streams
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DAC
2003
ACM
15 years 2 months ago
Low-power design methodology for an on-chip bus with adaptive bandwidth capability
This paper describes a low-power design methodology for a bus architecture based on hybrid current/voltage mode signaling for deep sub-micrometer on-chip interconnects that achiev...
Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III
ACMACE
2007
ACM
15 years 1 months ago
Augmenting amusement rides with telemetry
We present a system that uses wireless telemetry to enhance the experience of fairground and theme park amusement rides. Our system employs wearable technologies to capture video,...
Brendan Walker, Holger Schnädelbach, Stefan R...
DRM
2007
Springer
15 years 3 months ago
Randomized radon transforms for biometric authentication via fingerprint hashing
We present a new technique for generating biometric fingerprint hashes, or summaries of information contained in human fingerprints. Our method calculates and aggregates various...
Mariusz H. Jakubowski, Ramarathnam Venkatesan
HPDC
2002
IEEE
15 years 2 months ago
A High-Performance Cluster Storage Server
An essential building block for any Data Grid infrastructure is the storage server. In this paper we describe a high-performance cluster storage server built around the SDSC Stora...
Keith Bell, Andrew A. Chien, Mario Lauria
EUROPAR
2010
Springer
14 years 9 months ago
Optimized On-Chip-Pipelined Mergesort on the Cell/B.E
Abstract. Limited bandwidth to off-chip main memory is a performance bottleneck in chip multiprocessors for streaming computations, such as Cell/B.E., and this will become even mor...
Rikard Hultén, Christoph W. Kessler, Jö...