33 search results - page 3 / 7 » Meta-heuristics for Circuit Partitioning in Parallel Test Ge... |
EURODAC
1994
IEEE
13 years 10 months ago
1994
IEEE
This paper presents a multiple-FPGA-based experimentation board. The problem to be solved is that of implementing a circuit into a set of FPGAs. This board provides a hardware env...
VLSID
2009
IEEE
14 years 6 months ago
2009
IEEE
We present the automatic test pattern generator TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully ...
ETS
2006
IEEE
14 years 10 days ago
2006
IEEE
A central problem in built-in self test (BIST) is how to efficiently generate a small set of test vectors that detect all targeted faults. We propose a novel solution that uses l...
ICCAD
2009
IEEE
13 years 4 months ago
2009
IEEE
A parallel computing approach for large-scale SPICE-accurate circuit simulation is described that is based on a new preconditioned iterative solver. The preconditioner involves the...
DSD
2007
IEEE
14 years 19 days ago
2007
IEEE
This paper discusses possibilities for a choice of a pseudorandom pattern generator that is to be used in combination with the column-matching based built-in self-test design meth...