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» MetaCores: Design and Optimization Techniques
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87
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DDECS
2008
IEEE
137views Hardware» more  DDECS 2008»
15 years 4 months ago
Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on Chip
Abstract—In Network-on-Chip (NoC) application design, coreto-node mapping is an important but intractable optimization problem. In the paper, we use simulated annealing to tackle...
Zhonghai Lu, Lei Xia, Axel Jantsch
66
Voted
ICOIN
2005
Springer
15 years 3 months ago
Decreasing Mobile IPv6 Signaling with XCAST
Abstract. Mobile IPv6 is the IETF proposition to support host mobility in the Internet. It provides routing optimization for packets sent to the mobile node at the expense of signa...
Thierry Ernst
74
Voted
ISLPED
2004
ACM
123views Hardware» more  ISLPED 2004»
15 years 3 months ago
Improved clock-gating through transparent pipelining
This paper re-examines the well established clocking principles of pipelines. It is observed that clock gating techniques that have long been assumed optimal in reality produce a ...
Hans M. Jacobson
76
Voted
DFT
2002
IEEE
103views VLSI» more  DFT 2002»
15 years 3 months ago
Input Ordering in Concurrent Checkers to Reduce Power Consumption
A novel approach for reducing power consumption in checkers used for concurrent error detection is presented. Spatial correlations between the outputs of the circuit that drives t...
Kartik Mohanram, Nur A. Touba
68
Voted
EURODAC
1994
IEEE
186views VHDL» more  EURODAC 1994»
15 years 2 months ago
Algorithms for a switch module routing problem
We consider a switch module routing problem for symmetric array FPGAs. The work is motivated by two applications. The rst is that of eciently evaluating switch module designs [8]...
Shashidhar Thakur, D. F. Wong, S. Muthukrishnan