Sciweavers

2078 search results - page 365 / 416
» MetaCores: Design and Optimization Techniques
Sort
View
SC
1992
ACM
15 years 1 months ago
Compiler Code Transformations for Superscalar-Based High Performance Systems
Exploiting parallelism at both the multiprocessor level and the instruction level is an e ective means for supercomputers to achieve high-performance. The amount of instruction-le...
Scott A. Mahlke, William Y. Chen, John C. Gyllenha...
CASES
2007
ACM
15 years 1 months ago
Fragment cache management for dynamic binary translators in embedded systems with scratchpad
Dynamic binary translation (DBT) has been used to achieve numerous goals (e.g., better performance) for general-purpose computers. Recently, DBT has also attracted attention for e...
José Baiocchi, Bruce R. Childers, Jack W. D...
DMSN
2007
ACM
15 years 1 months ago
Declarative temporal data models for sensor-driven query processing
Many sensor network applications monitor continuous phenomena by sampling, and fit time-varying models that capture the phenomena's behaviors. We introduce Pulse, a framework...
Yanif Ahmad, Ugur Çetintemel
ARVLSI
2001
IEEE
289views VLSI» more  ARVLSI 2001»
15 years 1 months ago
A High-Performance 64-bit Adder Implemented in Output Prediction Logic
Output Prediction Logic (OPL) is a technique that can be applied to conventional CMOS logic families to obtain considerable speedups. When applied to static CMOS, OPL retains the ...
Sheng Sun, Larry McMurchie, Carl Sechen
CGO
2003
IEEE
15 years 1 months ago
METRIC: Tracking Down Inefficiencies in the Memory Hierarchy via Binary Rewriting
In this paper, we present METRIC, an environment for determining memory inefficiencies by examining data traces. METRIC is designed to alter the performance behavior of applicatio...
Jaydeep Marathe, Frank Mueller, Tushar Mohan, Bron...