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» MetaCores: Design and Optimization Techniques
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GLVLSI
2009
IEEE
164views VLSI» more  GLVLSI 2009»
15 years 4 months ago
Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip
In the context of nanoscale networks-on-chip (NoCs), each link implementation solution is not just a specific synthesis optimization technique with local performance and power im...
Daniele Ludovici, Georgi Nedeltchev Gaydadjiev, Da...
ASPDAC
2005
ACM
107views Hardware» more  ASPDAC 2005»
14 years 11 months ago
Making fast buffer insertion even faster via approximation techniques
Abstract— As technology scales to 0.13 micron and below, designs are requiring buffers to be inserted on interconnects of even moderate length for both critical paths and fixing...
Zhuo Li, Cliff C. N. Sze, Charles J. Alpert, Jiang...
IH
2001
Springer
15 years 2 months ago
Computational Forensic Techniques for Intellectual Property Protection
Computational forensic engineering (CFE) aims to identify the entity that created a particular intellectual property (IP). Rather than relying on watermarking content or designs, t...
Jennifer L. Wong, Darko Kirovski, Miodrag Potkonja...
ICASSP
2009
IEEE
15 years 4 months ago
Efficacy of a constantly adaptive language modeling technique for web-scale applications
In this paper, we describe CALM, a method for building statistical language models for the Web. CALM addresses several unique challenges dealing with the Web contents. First, CALM...
Kuansan Wang, Xiaolong Li
VTS
2008
IEEE
104views Hardware» more  VTS 2008»
15 years 4 months ago
Signature Rollback - A Technique for Testing Robust Circuits
Dealing with static and dynamic parameter variations has become a major challenge for design and test. To avoid unnecessary yield loss and to ensure reliable system operation a ro...
Uranmandakh Amgalan, Christian Hachmann, Sybille H...