2078 search results - page 65 / 416 » MetaCores: Design and Optimization Techniques |
DAC
2000
ACM
15 years 2 months ago
2000
ACM
In many modern designs, timing is either a key optimization goal and/or a mandatory constraint. We propose the first intellectual property protection technique using watermarking ...
ASPDAC
2001
ACM
15 years 1 months ago
2001
ACM
We propose a timing optimization technique for a complex finite state machine that consists of not only random logic but also data operators. In such a design, the timing critical...
FPGA
2008
ACM
14 years 11 months ago
2008
ACM
Logical effort (LE) is a linear technique for modelling the delay of a circuit in a technology independent manner. It offers the potential to simplify delay models for FPGAs and g...
ICCD
2007
IEEE
15 years 4 months ago
2007
IEEE
A methodology for constructing circuit-level mismatch models and performing yield optimization is presented for CMOS analog circuits. The methodology combines statistical techniqu...
ICCAD
1999
IEEE
15 years 2 months ago
1999
IEEE
This paper addresses an optimal technique for throughput optimization of general non-linear data flow computations using a set of transformations. Throughput is widely recognized ...