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» MetaCores: Design and Optimization Techniques
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DATE
2009
IEEE
122views Hardware» more  DATE 2009»
15 years 6 months ago
Analysis and optimization of NBTI induced clock skew in gated clock trees
NBTI (Negative Bias Temperature Instability) has emerged as the dominant PMOS device failure mechanism for sub100nm VLSI designs. There is little research to quantify its impact o...
Ashutosh Chakraborty, Gokul Ganesan, Anand Rajaram...
ICCAD
2007
IEEE
139views Hardware» more  ICCAD 2007»
15 years 6 months ago
Using functional independence conditions to optimize the performance of latency-insensitive systems
—In latency-insensitive design shell modules are used to encapsulate system components (pearls) in order to interface them with the given latency-insensitive protocol and dynamic...
Cheng-Hong Li, Luca P. Carloni
FPL
2005
Springer
100views Hardware» more  FPL 2005»
15 years 5 months ago
Power and Area Optimization for Multiple Restricted Multiplication
This paper presents a design and optimization technique for the Multiple Restricted Multiplication problem [1]. This refers to a situation where a single variable is multiplied by...
Nalin Sidahao, George A. Constantinides, Peter Y. ...
CEC
2005
IEEE
15 years 5 months ago
Sequential parameter optimization
Abstract- Sequential parameter optimization is a heuristic that combines classical and modern statistical techniques to improve the performance of search algorithms. To demonstrate...
Thomas Bartz-Beielstein, Christian Lasarczyk, Mike...
ICCAD
1997
IEEE
86views Hardware» more  ICCAD 1997»
15 years 4 months ago
Interconnect design for deep submicron ICs
Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends...
Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok K...