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VLSID
2005
IEEE
285views VLSI» more  VLSID 2005»
15 years 11 months ago
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan,...
VLSID
2003
IEEE
183views VLSI» more  VLSID 2003»
15 years 11 months ago
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks
We present an innovative design of an accurate, 2D DCT IDCT processor, which handles scaled and sub-sampled input blocks efficiently. In the IDCT mode, the latency of the processo...
Rohini Krishnan, Om Prakash Gangwal, Jos T. J. van...
VLSID
2001
IEEE
200views VLSI» more  VLSID 2001»
15 years 11 months ago
Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures
The emergence of several communication architectures for System-on-Chips provides designers with a variety of design alternatives. In addition, the need to customize the system ar...
Kanishka Lahiri, Sujit Dey, Anand Raghunathan
CHI
2004
ACM
15 years 11 months ago
Story lifecycle in a product development organization
This poster describes an integrated set of stories and story-based activities that we have used in product development in IBM Software Group's Lotus product organizations. We...
Majie Zeller, Sandra L. Kogan, Michael J. Muller, ...
POPL
2004
ACM
15 years 11 months ago
Atomizer: a dynamic atomicity checker for multithreaded programs
Ensuring the correctness of multithreaded programs is difficult, due to the potential for unexpected interactions between concurrent threads. Much previous work has focused on det...
Cormac Flanagan, Stephen N. Freund