254 search results - page 21 / 51 » Methods for complex single-mind architecture designs |
100
Voted
MICRO
2003
IEEE
15 years 2 months ago
2003
IEEE
Single-event upsets from particle strikes have become a key challenge in microprocessor design. Techniques to deal with these transient faults exist, but come at a cost. Designers...
FMCO
2007
Springer
15 years 3 months ago
2007
Springer
This paper describes the architecture of costa, an abstract interpretation based cost and termination analyzer for Java bytecode. The system receives as input a bytecode program, (...
DAC
1995
ACM
15 years 1 months ago
1995
ACM
- Power estimation in combinational modules is addressed from a probabilistic point of view. The zero-delay hypothesis is considered and under highly correlated input streams, the ...
98
Voted
DAC
1994
ACM
15 years 1 months ago
1994
ACM
-- In previous work, Hu and Dill identified a common cause of BDD-size blowup in high-level design verification and proposed the method of implicitly conjoined invariants to addres...
107
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DAC
2004
ACM
15 years 1 months ago
2004
ACM
This paper presents new technology that accelerates system verification. Traditional methods for verifying functional designs are based on logic simulation, which becomes more tim...