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» Methods for complex single-mind architecture designs
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DATE
2009
IEEE
107views Hardware» more  DATE 2009»
15 years 4 months ago
Learning early-stage platform dimensioning from late-stage timing verification
— Today's innovations in the automotive sector are, to a great extent, based on electronics. The increasing integration complexity and stringent cost reduction goals turn E/...
Kai Richter, Marek Jersak, Rolf Ernst
DAC
2005
ACM
15 years 10 months ago
Structure preserving reduction of frequency-dependent interconnect
A rational Arnoldi method for passivity-preserving model-order reduction (MOR) with implicit multi-point moment matching for systems with frequency-dependent interconnects is desc...
Quming Zhou, Kartik Mohanram, Athanasios C. Antoul...
ISSS
2000
IEEE
290views Hardware» more  ISSS 2000»
15 years 2 months ago
Mapping Array Communication onto FIFO Communication - Towards an Implementation
In high-throughput real-time media processing systems, the communication between processing units is typically specified as multi-dimensional arrays. However, the implementation ...
Jeffrey Kang, Albert van der Werf, Paul E. R. Lipp...
DAC
2003
ACM
15 years 2 months ago
Advanced techniques for RTL debugging
Conventional register transfer level (RTL) debugging is based on overlaying simulation results on structural connectivity information of the Hardware Description Language (HDL) so...
Yu-Chin Hsu, Bassam Tabbara, Yirng-An Chen, Fur-Sh...
DAC
2006
ACM
15 years 10 months ago
Efficient detection and exploitation of infeasible paths for software timing analysis
Accurate estimation of the worst-case execution time (WCET) of a program is important for real-time embedded software. Static WCET estimation involves program path analysis and ar...
Vivy Suhendra, Tulika Mitra, Abhik Roychoudhury, T...