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ASPDAC
2004
ACM
97views Hardware» more  ASPDAC 2004»
15 years 10 months ago
Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost
As gate delays decrease faster than wire delays for each technology generation, buffer insertion becomes a popular method to reduce the interconnect delay. Several modern buffer in...
Weiping Shi, Zhuo Li, Charles J. Alpert
SAC
2010
ACM
15 years 9 months ago
User-controlled generalization boundaries for p-sensitive k-anonymity
Numerous privacy models based on the k-anonymity property have been introduced in the last few years. While differing in their methods and quality of their results, they all focus...
Alina Campan, Traian Marius Truta, Nicholas Cooper
VISUALIZATION
2000
IEEE
15 years 9 months ago
Hardware-accelerated volume and isosurface rendering based on cell-projection
We present two beneficial rendering extensions to the Projected Tetrahedra (PT) algorithm by Shirley and Tuchman. These extensions are compatible with any cell sorting technique,...
Stefan Röttger, Martin Kraus, Thomas Ertl
GECCO
2008
Springer
137views Optimization» more  GECCO 2008»
15 years 5 months ago
Evolutionary path planner for UAVs in realistic environments
This paper presents a path planner for Unmanned Air Vehicles (UAVs) based on Evolutionary Algorithms (EA) that can be used in realistic risky scenarios. The path returned by the a...
Jesús Manuel de la Cruz, Eva Besada-Portas,...
TCAD
2008
100views more  TCAD 2008»
15 years 4 months ago
Robust Clock Tree Routing in the Presence of Process Variations
Abstract--Advances in very large-scale integration technology make clock skew more susceptible to process variations. Notwithstanding efficient exact zero-skew algorithms, clock sk...
Uday Padmanabhan, Janet Meiling Wang, Jiang Hu