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DAC
2003
ACM
16 years 22 days ago
Test cost reduction for SOCs using virtual TAMs and lagrange multipliers
Recent advances in tester technology have led to automatic test equipment (ATE) that can operate at up to several hundred MHz. However, system-on-chip (SOC) scan chains typically ...
Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski,...
DATE
2007
IEEE
100views Hardware» more  DATE 2007»
15 years 6 months ago
SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling
Abstract— We present an SoC testing approach that integrates test data compression, TAM/test wrapper design, and test scheduling. An improved LFSR reseeding technique is used as ...
Zhanglei Wang, Krishnendu Chakrabarty, Seongmoon W...
DATE
2008
IEEE
85views Hardware» more  DATE 2008»
15 years 6 months ago
Video Processing Requirements on SoC Infrastructures
Applications from the embedded consumer domain put challenging requirements on SoC infrastructures, i.e. interconnect and memory. Specifically, video applications demand large sto...
Pieter van der Wolf, Tomas Henriksson
IEEEPACT
2000
IEEE
15 years 4 months ago
aSOC: A Scalable, Single-Chip Communications Architecture
As on-chip integration matures, single-chip system designers must not only be concerned with component-level issues such as performance and power, but also with onchip system-leve...
Jian Liang, Sriram Swaminathan, Russell Tessier
DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
15 years 6 months ago
A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing
1-The increasing cost for System-on-Chip (SOC) testing is mainly due to the huge test data volumes that lead to long test application time and require large automatic test equipmen...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...