109 search results - page 21 / 22 » Microcode Generation for Flexible Parallel Target Architectu... |
100
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ICS
2004
Tsinghua U.
15 years 5 months ago
2004
Tsinghua U.
The Cray X1 was recently introduced as the first in a new line of parallel systems to combine high-bandwidth vector processing with an MPP system architecture. Alongside capabili...
HPDC
2010
IEEE
15 years 23 days ago
2010
IEEE
MapReduce offers a flexible programming model for processing and generating large data sets on dedicated resources, where only a small fraction of such resources are every unavaila...
173
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SIGMOD
2007
ACM
15 years 11 months ago
2007
ACM
Two trends are converging to make the CPU cost of a table scan a more important component of database performance. First, table scans are becoming a larger fraction of the query p...
129
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IWOMP
2007
Springer
15 years 5 months ago
2007
Springer
The Cell processor is a heterogeneous multi-core processor with one Power Processing Engine (PPE) core and eight Synergistic Processing Engine (SPE) cores. Each SPE has a directly...
107
Voted
DATE
2010
IEEE
15 years 4 months ago
2010
IEEE
—Multi-Processor System-on-Chips (MPSoCs) exploit task-level parallelism to achieve high computation throughput, but concurrent memory accesses from multiple PEs may cause memory...