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GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
15 years 5 months ago
A first look at the interplay of code reordering and configurable caches
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
INFSOF
2006
66views more  INFSOF 2006»
14 years 11 months ago
Scenario-based multitasking for real-time object-oriented models
Contemporary embedded systems quite often employ extremely complicated software consisting of a number of interrelated components, and this has made object-oriented design methodo...
Saehwa Kim, Jiyong Park, Seongsoo Hong
CASES
2008
ACM
15 years 1 months ago
Reducing pressure in bounded DBT code caches
Dynamic binary translators (DBT) have recently attracted much attention for embedded systems. The effective implementation of DBT in these systems is challenging due to tight cons...
José Baiocchi, Bruce R. Childers, Jack W. D...
ANCS
2005
ACM
15 years 5 months ago
Resource mapping and scheduling for heterogeneous network processor systems
Task to resource mapping problems are encountered during (i) hardware-software co-design and (ii) performance optimization of Network Processor systems. The goal of the first pro...
Liang Yang, Tushar Gohad, Pavel Ghosh, Devesh Sinh...
DAC
2002
ACM
16 years 21 days ago
A fast on-chip profiler memory
Profiling an application executing on a microprocessor is part of the solution to numerous software and hardware optimization and design automation problems. Most current profilin...
Roman L. Lysecky, Susan Cotterell, Frank Vahid