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PARLE
1987
15 years 28 days ago
Emulating Digital Logic using Transputer Networks (very High Parallelism = Simplicity = Performance)
Modern VLSI technology has changed the economic rules by which the balance between processing power, memory and communications is decided in computing systems. This will have a pr...
Peter H. Welch
IPPS
2000
IEEE
15 years 1 months ago
Micro-Architectures of High Performance, Multi-User System Area Network Interface Cards
This paper examines two Network Interface Card microarchitectures that support low latency, high bandwidth userlevel message passing in multi-user environments. The two are at dif...
Boon Seong Ang, Derek Chiou, Larry Rudolph, Arvind
HPCA
2009
IEEE
15 years 10 months ago
Versatile prediction and fast estimation of Architectural Vulnerability Factor from processor performance metrics
The shrinking processor feature size, lower threshold voltage and increasing clock frequency make modern processors highly vulnerable to transient faults. Architectural Vulnerabil...
Lide Duan, Bin Li, Lu Peng
CSC
2010
14 years 7 months ago
An Evaluation of Parallel Knapsack Algorithms on Multicore Architectures
Emergence of chip multiprocessor systems has dramatically increased the performance potential of computer systems. Since the amount of exploited parallelism is directly influenced ...
Hammad Rashid, Clara Novoa, Apan Qasem
HICSS
2009
IEEE
103views Biometrics» more  HICSS 2009»
15 years 4 months ago
A Thin Client Interface to a High Performance Multi-modal Image Analytics System
We describe a platform for performing text and radiology analytics (TARA). We integrate commercially available hardware and middleware components to construct an environment which...
James W. Cooper, Shahram Ebadollahi, Ellen Eide