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ICPADS
2006
IEEE
15 years 5 months ago
Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new...
Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edw...
NCA
2007
IEEE
15 years 6 months ago
GORDA: An Open Architecture for Database Replication
Although database replication has been a standard feature in database management systems for a long time, third party solutions have been enjoying an increasing popularity. These ...
Alfrânio Correia Jr., José Pereira, L...
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SC
2004
ACM
15 years 5 months ago
Analysis and Performance Results of a Molecular Modeling Application on Merrimac
The Merrimac supercomputer uses stream processors and a highradix network to achieve high performance at low cost and low power. The stream architecture matches the capabilities o...
Mattan Erez, Jung Ho Ahn, Ankit Garg, William J. D...
IPPS
2009
IEEE
15 years 6 months ago
Implementing OpenMP on a high performance embedded multicore MPSoC
In this paper we discuss our initial experiences adapting OpenMP to enable it to serve as a programming model for high performance embedded systems. A high-level programming model...
Barbara M. Chapman, Lei Huang, Eric Biscondi, Eric...
DSN
2000
IEEE
15 years 4 months ago
OFTT: A Fault Tolerance Middleware Toolkit for Process Monitoring and Control Windows NT Applications
This paper describes the OFTT (OLE Fault Tolerance Technology), a fault tolerance middleware toolkit running on the Microsoft Windows NT operating system that provides required fa...
Myron Hecht, Xuegao An, Bing Zhang, Yutao He