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GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
15 years 8 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
117
Voted
DAC
2009
ACM
16 years 4 months ago
Speculation in elastic systems
Speculation is a well-known technique for increasing parallelism of the microprocessor pipelines and hence their performance. While implementing speculation in modern design pract...
Marc Galceran Oms, Jordi Cortadella, Michael Kishi...
138
Voted
ICCD
2005
IEEE
159views Hardware» more  ICCD 2005»
15 years 9 months ago
Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors
Nanoelectronic devices are expected to have extremely high and variable fault rates; thus future processor architectures based on these unreliable devices need to be built with fa...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
VLSID
2004
IEEE
107views VLSI» more  VLSID 2004»
16 years 4 months ago
Performance Analysis of Inter Cluster Communication Methods in VLIW Architecture
With increasing demands for high performance by embedded systems, especially by digital signal processing applications, embedded processors must increase available instruction lev...
Sourabh Saluja, Anshul Kumar
118
Voted
EUROSYS
2010
ACM
15 years 8 months ago
NOVA: a microhypervisor-based secure virtualization architecture
The availability of virtualization features in modern CPUs has reinforced the trend of consolidating multiple guest operating systems on top of a hypervisor in order to improve pl...
Udo Steinberg, Bernhard Kauer