649 search results - page 115 / 130 » Migrating to a real-time distributed parallel simulator arch... |
73
Voted
IEEEPACT
2008
IEEE
15 years 4 months ago
2008
IEEE
In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true ...
HPDC
2000
IEEE
15 years 2 months ago
2000
IEEE
While the MPP is still the most common architecture in supercomputer centers today, a simpler and cheaper machine configuration is growing increasingly common. This alternative s...
HPCA
2009
IEEE
15 years 10 months ago
2009
IEEE
Analytical modeling is an alternative to detailed performance simulation with the potential to shorten the development cycle and provide additional insights. This paper proposes a...
ICS
2001
Tsinghua U.
15 years 2 months ago
2001
Tsinghua U.
The caching behavior of multimedia applications has been described as having high instruction reference locality within small loops, very large working sets, and poor data cache p...
PPOPP
2010
ACM
15 years 7 months ago
2010
ACM
Most modern Chip Multiprocessors (CMP) feature shared cache on chip. For multithreaded applications, the sharing reduces communication latency among co-running threads, but also r...