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ISCAS
2005
IEEE
132views Hardware» more  ISCAS 2005»
15 years 3 months ago
A high performance distributed-parallel-processor architecture for 3D IIR digital filters
—Real-time spatio-temporal VLSI 3D IIR digital filters may be used for imaging or beamforming applications employing 3D input signals from synchronously-sampled multi-sensor arra...
Arjuna Madanayake, Leonard T. Bruton
VECPAR
1998
Springer
15 years 1 months ago
Simulating Magnetised Plasma with the Versatile Advection Code
Abstract. Matter in the universe mainly consists of plasma. The dynamics of plasmas is controlled by magnetic fields. To simulate the evolution of magnetised plasma, we solve the e...
Rony Keppens, Gábor Tóth
HPCC
2005
Springer
15 years 3 months ago
Memory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture
In this paper we present an exhaustive evaluation of the memory subsystem in a chip-multiprocessor (CMP) architecture composed of 16 cores. The characterization is performed making...
Francisco J. Villa, Manuel E. Acacio, José ...
IPPS
2010
IEEE
14 years 7 months ago
Improving numerical reproducibility and stability in large-scale numerical simulations on GPUs
The advent of general purpose graphics processing units (GPGPU's) brings about a whole new platform for running numerically intensive applications at high speeds. Their multi-...
Michela Taufer, Omar Padron, Philip Saponaro, Sand...
IPPS
2006
IEEE
15 years 3 months ago
Dynamically reconfigurable cache architecture using adaptive block allocation policy
In this paper, we present a dynamically reconfigurable cache architecture using adaptive block allocation policy analyzed by means of simulation. Our main objectives are: to propo...
Milene Barbosa Carvalho, Luís Fabríc...