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IPPS
2009
IEEE
15 years 4 months ago
Throughput-fairness tradeoff in Best Effort flow control for on-chip architectures
We consider two flow control schemes for Best Effort traffic in on-chip architectures, which can be deemed as the solutions to the boundary extremes of a class of utility maximi...
Fahimeh Jafari, Mohammad Sadegh Talebi, Mohammad H...
IPPS
1998
IEEE
15 years 2 months ago
HIPIQS: A High-Performance Switch Architecture Using Input Queuing
Switch-based interconnects are used in a number of application domains including parallel system interconnects, local area networks, and wide area networks. However, very few swit...
Rajeev Sivaram, Craig B. Stunkel, Dhabaleswar K. P...
WOSP
1998
ACM
15 years 1 months ago
Poems: end-to-end performance design of large parallel adaptive computational systems
The POEMS project is creating an environment for end-to-end performance modeling of complex parallel and distributed systems, spanning the domains of application software, runti...
Ewa Deelman, Aditya Dube, Adolfy Hoisie, Yong Luo,...
HPCC
2009
Springer
15 years 2 months ago
A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures
—The potential for destructive interference between running processes is increased as Chip Multiprocessors (CMPs) share more on-chip resources. We believe that understanding the ...
Magnus Jahre, Marius Grannæs, Lasse Natvig
ICPADS
1994
IEEE
15 years 1 months ago
Efficient Fault Tolerance: An Approach to Deal with Transient Faults in Multiprocessor Architectures
Dynamic error processing approaches are an important mechanism to increase the reliability in a multiprocessor system, while making efficient use of the available resources. To th...
Andrea Bondavalli, Silvano Chiaradonna, Felicita D...