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ICPP
2008
IEEE
15 years 4 months ago
Optimizing Issue Queue Reliability to Soft Errors on Simultaneous Multithreaded Architectures
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
Xin Fu, Wangyuan Zhang, Tao Li, José A. B. ...
MAGS
2007
115views more  MAGS 2007»
14 years 9 months ago
Designing modular architectures in the framework AKIRA
AKIRA is an open source framework designed for parallel, asynchronous and distributed computation, on the basis of some general architectural principles which are inspired by modu...
Giovanni Pezzulo, Gianguglielmo Calvi
VLSID
2006
IEEE
153views VLSI» more  VLSID 2006»
15 years 10 months ago
An Asynchronous Interconnect Architecture for Device Security Enhancement
We present a new style of long-distance, on-chip interconnect, based loosely on the asynchronous GasP architecture. It has a number of advantages over conventional designs, the mo...
Simon Hollis, Simon W. Moore
HPCA
2001
IEEE
15 years 10 months ago
Automatically Mapping Code on an Intelligent Memory Architecture
This paper presents an algorithm to automatically map code on a generic intelligent memory system that consists of a host processor and a simpler memory processor. To achieve high...
Jaejin Lee, Yan Solihin, Josep Torrellas
NPC
2005
Springer
15 years 3 months ago
Performance Modelling and Optimization of Memory Access on Cellular Computer Architecture Cyclops64
This paper focuses on the Cyclops64 computer architecture and presents an analytical model and performance simulation results for the preloading and loop unrolling approaches to op...
Yanwei Niu, Ziang Hu, Kenneth E. Barner, Guang R. ...