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1999
Tsinghua U.
15 years 1 months ago
Realizing the performance potential of the virtual interface architecture
The Virtual Interface (VI) Architecture provides protected userlevel communication with high delivered bandwidth and low permessage latency, particularly for small messages. The V...
Evan Speight, Hazim Abdel-Shafi, John K. Bennett
CAL
2010
14 years 6 months ago
SMT-Directory: Efficient Load-Load Ordering for SMT
Memory models like SC, TSO, and PC enforce load-load ordering, requiring that loads from any single thread appear to occur in program order to all other threads. Out-of-order execu...
A. Hilton, A. Roth
72
Voted
IPPS
2009
IEEE
15 years 4 months ago
Design, implementation, and evaluation of transparent pNFS on Lustre
Parallel NFS (pNFS) is an emergent open standard for parallelizing data transfer over a variety of I/O protocols. Prototypes of pNFS are actively being developed by industry and a...
Weikuan Yu, Oleg Drokin, Jeffrey S. Vetter
CODES
2004
IEEE
15 years 1 months ago
A loop accelerator for low power embedded VLIW processors
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performan...
Binu K. Mathew, Al Davis
78
Voted
WWW
2005
ACM
15 years 10 months ago
A publish and subscribe collaboration architecture for web-based information
Markup languages, representations, schemas, and tools have significantly increased the ability for organizations to share their information. Languages, such as the Extensible Mark...
M. Brian Blake, David H. Fado, Gregory A. Mack