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ISSS
1999
IEEE
109views Hardware» more  ISSS 1999»
15 years 1 months ago
Loop Alignment for Memory Accesses Optimization
Portable or embedded systems allow more and more complex applications like multimedia today. These applications and submicronic technologies have made the power consumption criter...
Antoine Fraboulet, Guillaume Huard, Anne Mignotte
BIRTHDAY
2006
Springer
15 years 1 months ago
Verification by Parallelization of Parametric Code
Abstract. Loops and other unbound control structures constitute a major bottleneck in formal software verification, because correctness proofs over such control structures generall...
Tobias Gedell, Reiner Hähnle
ENTCS
2002
166views more  ENTCS 2002»
14 years 9 months ago
Translation and Run-Time Validation of Optimized Code
The paper presents approaches to the validation of optimizing compilers. The emphasis is on aggressive and architecture-targeted optimizations which try to obtain the highest perf...
Lenore D. Zuck, Amir Pnueli, Yi Fang, Benjamin Gol...
ISHPC
2003
Springer
15 years 2 months ago
Code and Data Transformations for Improving Shared Cache Performance on SMT Processors
Simultaneous multithreaded processors use shared on-chip caches, which yield better cost-performance ratios. Sharing a cache between simultaneously executing threads causes excessi...
Dimitrios S. Nikolopoulos
PC
1998
153views Management» more  PC 1998»
14 years 9 months ago
Compilation Techniques for Out-of-Core Parallel Computations
The difficulty of handling out-of-core data limits the performance of supercomputers as well as the potential of the parallel machines. Since writing an efficient out-of-core ve...
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanuja...