58 search results - page 10 / 12 » Minimal Delay Interconnect Design Using Alphabetic Trees |
JETC
2008
14 years 8 months ago
2008
With aggressive reductions in feature sizes and the integration of multiple functionalities on the same die, bottlenecks due to I/O pin limitations have become a severe issue in to...
ICC
2007
IEEE
15 years 3 months ago
2007
IEEE
— We target M-ary data sequence estimation over time-variant frequency selective fading channels subject to cochannel interference (CCI). A novel joint reduced state sequence est...
103
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ICCAD
1997
IEEE
15 years 1 months ago
1997
IEEE
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...
ICCAD
2007
IEEE
15 years 6 months ago
2007
IEEE
Abstract— This paper addresses the module assignment problem in pinlimited designs under the stacked-Vdd circuit paradigm. A partition-based algorithm is presented for efficient...
107
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GLVLSI
2009
IEEE
15 years 4 months ago
2009
IEEE
In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a...