58 search results - page 3 / 12 » Minimal Delay Interconnect Design Using Alphabetic Trees |
ISCAS
1995
IEEE
15 years 1 months ago
1995
IEEE
We present a novel technique for datapath allocation, which incorporates interconnection area and delay estimates based on dynamic oorplanning. In this approach, datapath area is ...
DAC
1999
ACM
15 years 1 months ago
1999
ACM
As the CMOS technology enters the deep submicron design era, the lateral inter-wire coupling capacitance becomes the dominant part of load capacitance and makes RC delay on the bu...
DAC
2005
ACM
15 years 10 months ago
2005
ACM
This paper presents a novel repeater insertion algorithm for the power minimization of realistic interconnect trees under given timing budgets. Our algorithm judiciously combines ...
ICIP
2003
IEEE
15 years 11 months ago
2003
IEEE
This paper proposes a new method of designing finitesupport wavelet filters, based on minimization of energy in key parts of the frequency domain. In particular this technique is ...
DAC
2003
ACM
15 years 2 months ago
2003
ACM
This paper describes a low-power design methodology for a bus architecture based on hybrid current/voltage mode signaling for deep sub-micrometer on-chip interconnects that achiev...