58 search results - page 4 / 12 » Minimal Delay Interconnect Design Using Alphabetic Trees |
DSD
2007
IEEE
15 years 3 months ago
2007
IEEE
Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the ...
ICCAD
1994
IEEE
15 years 1 months ago
1994
IEEE
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
ICCAD
1998
IEEE
15 years 1 months ago
1998
IEEE
In this paper we present a new fanout optimization algorithm which is particularly suitable for digital circuits designed with submicron CMOS technologies. Restricting the class o...
ISLPED
2005
ACM
15 years 3 months ago
2005
ACM
In this paper, we propose joint repeater insertion and crosstalk avoidance coding as a low-power alternative to repeater insertion for global bus design in nanometer technologies....
ICCD
2004
IEEE
15 years 6 months ago
2004
IEEE
In this paper, we propose a combined channel segmentation and buffer insertion approach, which minimizes the number of buffers inserted while satisfying the delay constraints for ...