58 search results - page 5 / 12 » Minimal Delay Interconnect Design Using Alphabetic Trees |
ICCAD
2004
IEEE
15 years 6 months ago
2004
IEEE
Traditional timing-driven placement considers only combinational delays and does not take into account the potential of subsequent sequential optimization steps. As a result, the ...
113
click to vote
APPROX
2008
Springer
14 years 11 months ago
2008
Springer
Abstract. We give a (ln n + 1)-approximation for the decision tree (DT) problem. An instance of DT is a set of m binary tests T = (T1, . . . , Tm) and a set of n items X = (X1, . ....
TC
2008
14 years 9 months ago
2008
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
DATE
2010
IEEE
14 years 8 months ago
2010
IEEE
Abstract—On-chip interconnection network is a crucial design component in high-performance System-on-Chips (SoCs). Many of previous works have focused on the automation of its to...
ISLPED
2006
ACM
15 years 3 months ago
2006
ACM
—The thermal gradients existing in high-performance circuits may significantly affect their timing behavior, in particular, by increasing the skew of the clock net and/or alteri...