58 search results - page 9 / 12 » Minimal Delay Interconnect Design Using Alphabetic Trees |
INTEGRATION
2008
14 years 9 months ago
2008
Thermal gradients across the die are becoming increasingly prominent as we scale further down into the sub-nanometer regime. While temperature was never a primary concern, its non...
CODES
2006
IEEE
15 years 3 months ago
2006
IEEE
When designing a System-on-Chip (SoC) using a Networkon-Chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power ...
ICCAD
2002
IEEE
15 years 6 months ago
2002
IEEE
We propose to introduce redundant interconnects for manufacturing yield and reliability improvement. By introducing redundant interconnects, the potential for open faults is reduc...
DAC
2005
ACM
15 years 10 months ago
2005
ACM
As technology advances into the nanometer territory, the interconnect delay has become a first-order effect on chip performance. To handle this effect, the X-architecture has been...
ICCAD
2009
IEEE
14 years 7 months ago
2009
IEEE
With increasing process variation, binning has become an important technique to improve the values of fabricated chips, especially in high performance microprocessors where transpa...