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ICCAD
1997
IEEE
90views Hardware» more  ICCAD 1997»
15 years 1 months ago
A hierarchical decomposition methodology for multistage clock circuits
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar
DAC
1997
ACM
15 years 1 months ago
Wire Segmenting for Improved Buffer Insertion
Buffer insertion seeks to place buffers on the wires of a signal net to minimize delay. Van Ginneken [14] proposed an optimal dynamic programming solution (with extensions propose...
Charles J. Alpert, Anirudh Devgan
GLVLSI
1996
IEEE
125views VLSI» more  GLVLSI 1996»
15 years 1 months ago
Performance-Driven Interconnect Global Routing
In this paper, we propose a global routing algorithm for multi-layer building-block layouts. The algorithm is based on successive ripup and rerouting while satisfying edge capacit...
Dongsheng Wang, Ernest S. Kuh
FSTTCS
1993
Springer
15 years 1 months ago
Compact Location Problems
We investigate the complexity and approximability of some location problems when two distance values are specified for each pair of potential sites. These problems involve the se...
Venkatesh Radhakrishnan, Sven Oliver Krumke, Madha...
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GLOBECOM
2009
IEEE
15 years 1 months ago
Near-ML Detection over a Reduced Dimension Hypersphere
Abstract--In this paper, we propose a near-maximum likelihood (ML) detection method referred to as reduced dimension ML search (RD-MLS). The RD-MLS detector is based on a partition...
Jun Won Choi, Byonghyo Shim, Andrew C. Singer