5506 search results - page 235 / 1102 » Minimal Logic Programs |
137
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ASPDAC
2005
ACM
15 years 9 months ago
2005
ACM
: In ultra-deep submicron VLSI circuits, clock network is a major source of power consumption and power supply noise. Therefore, it is very important to minimize clock network size...
126
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ENTCS
2002
15 years 4 months ago
2002
We compare Meyer and Routley's minimal relevant logic B+ with the recent semanticsbased approach to subtyping introduced by Frisch, Castagna and Benzaken in the definition of...
112
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INFOCOM
2009
IEEE
15 years 11 months ago
2009
IEEE
—Packet classification is a function increasingly used in a number of networking appliances and applications. Typically, sists of a set of abstract classifications, and a set o...
136
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ICCAD
2006
IEEE
16 years 1 months ago
2006
IEEE
In a synchronous finite state machine (FSM), huge current peaks are often observed at the moment of state transition. Previous low power state encoding algorithms focus on the red...
136
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FPGA
2007
ACM
15 years 10 months ago
2007
ACM
This paper describes a technique that reduces dynamic power in FPGAs by reducing the number of glitches in the global routing resources. The technique involves adding programmable...