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GLVLSI
2003
IEEE
119views VLSI» more  GLVLSI 2003»
15 years 10 months ago
Simultaneous peak and average power minimization during datapath scheduling for DSP processors
The use of multiple supply voltages for energy and average power reduction is well researched and several works have appeared in the literature. However, in low power design using...
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappi...
SAC
2010
ACM
15 years 4 months ago
Efficient mapping and voltage islanding technique for energy minimization in NoC under design constraints
Voltage islanding technique in Network-on-Chip (NoC) can significantly reduce the computational energy consumption by scaling down the voltage levels of the processing elements (P...
Pavel Ghosh, Arunabha Sen
COR
2007
80views more  COR 2007»
15 years 4 months ago
Scheduling with tool changes to minimize total completion time under controllable machining conditions
Scheduling under controllable machining conditions has been studied for some time. Scheduling with tool changes, particularly due to tool wear, has just begun to receive attention...
M. Selim Akturk, Jay B. Ghosh, Rabia K. Kayan
JCO
2011
115views more  JCO 2011»
14 years 11 months ago
Approximation scheme for restricted discrete gate sizing targeting delay minimization
Discrete gate sizing is a critical optimization in VLSI circuit design. Given a set of available gate sizes, discrete gate sizing problem asks to assign a size to each gate such th...
Chen Liao, Shiyan Hu
ADAEUROPE
2004
Springer
15 years 10 months ago
High-Integrity Interfacing to Programmable Logic with Ada
Abstract. Programmable logic devices (PLDs) are now common components of safety-critical systems, and are increasingly used for safetyrelated or safety-critical functionality. Rece...
Adrian J. Hilton, Jon G. Hall