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ICCD
2008
IEEE
165views Hardware» more  ICCD 2008»
15 years 9 months ago
Analysis and minimization of practical energy in 45nm subthreshold logic circuits
Abstract— Over the last decade, the design of ultra-lowpower digital circuits in subthreshold regime has been driven by the quest for minimum energy per operation. In this contri...
David Bol, Renaud Ambroise, Denis Flandre, Jean-Di...
65
Voted
ICCAD
2004
IEEE
96views Hardware» more  ICCAD 2004»
15 years 9 months ago
M-trie: an efficient approach to on-chip logic minimization
Seraj Ahmad, Rabi N. Mahapatra
80
Voted
FSTTCS
2003
Springer
15 years 6 months ago
Minimality Results for the Spatial Logics
Daniel Hirschkoff, Étienne Lozes, Davide Sa...
84
Voted
VLSID
1998
IEEE
88views VLSI» more  VLSID 1998»
15 years 5 months ago
A Fast Two-level Logic Minimizer
P. Srinivasa Rao, James Jacob