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ISMVL
1999
IEEE
76views Hardware» more  ISMVL 1999»
15 years 5 months ago
Multiple-Valued Minimization to Optimize PLAs with Output EXOR Gates
This paper considers an optimization method of programmable logic arrays (PLAs), which have two-input EXOR gate at the outputs. The PLA realizes an EXOR of two sum-of-products exp...
Debatosh Debnath, Tsutomu Sasao
JELIA
2010
Springer
14 years 11 months ago
Parametrized Logic Programming
Traditionally, a logic program is built up to reason about atomic first-order formulas. The key idea of parametrized logic programming is that, instead of atomic first-order form...
Ricardo Gonçalves, José Júlio...
120
Voted
LPNMR
2001
Springer
15 years 5 months ago
plp: A Generic Compiler for Ordered Logic Programs
Abstract This paper describes a generic compiler, called plp, for translating ordered logic programs into standard logic programs under the answer set semantics. In an ordered logi...
James P. Delgrande, Torsten Schaub, Hans Tompits
VTS
2002
IEEE
138views Hardware» more  VTS 2002»
15 years 5 months ago
Test Power Reduction through Minimization of Scan Chain Transitions
Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test v...
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailog...
74
Voted
ITC
1999
IEEE
78views Hardware» more  ITC 1999»
15 years 5 months ago
Minimized power consumption for scan-based BIST
Power consumption of digital systems may increase significantly during testing. In this paper, systems equipped with a scan-based built-in self-test like the STUMPS architecture a...
Stefan Gerstendörfer, Hans-Joachim Wunderlich