This paper considers an optimization method of programmable logic arrays (PLAs), which have two-input EXOR gate at the outputs. The PLA realizes an EXOR of two sum-of-products exp...
Traditionally, a logic program is built up to reason about atomic first-order formulas. The key idea of parametrized logic programming is that, instead of atomic first-order form...
Abstract This paper describes a generic compiler, called plp, for translating ordered logic programs into standard logic programs under the answer set semantics. In an ordered logi...
Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test v...
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailog...
Power consumption of digital systems may increase significantly during testing. In this paper, systems equipped with a scan-based built-in self-test like the STUMPS architecture a...