1008 search results - page 186 / 202 » Minimizing Average Flow-Time |
ISCA
2007
IEEE
15 years 6 months ago
2007
IEEE
Due to wire delay scalability and bandwidth limitations inherent in shared buses and dedicated links, packet-switched on-chip interconnection networks are fast emerging as the per...
COCO
2007
Springer
15 years 5 months ago
2007
Springer
We examine the communication required for generating random variables remotely. One party Alice will be given a distribution D, and she has to send a message to Bob, who is then r...
101
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EMSOFT
2007
Springer
15 years 5 months ago
2007
Springer
Non-volatile RAM (NVRAM) such as PRAM (Phase-change RAM), FeRAM (Ferroelectric RAM), and MRAM (Magnetoresistive RAM) has characteristics of both non-volatile storage and random ac...
100
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HIPEAC
2007
Springer
15 years 5 months ago
2007
Springer
A critical component in the design of secure processors is memory encryption which provides protection for the privacy of code and data stored in off-chip memory. The overhead of ...
120
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ICS
2007
Tsinghua U.
15 years 5 months ago
2007
Tsinghua U.
Software or hardware data cache prefetching is an efficient way to hide cache miss latency. However effectiveness of the issued prefetches have to be monitored in order to maximi...