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144
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ICC
2007
IEEE
139views Communications» more  ICC 2007»
15 years 10 months ago
Joint Power and Channel Minimization in Topology Control: A Cognitive Network Approach
Abstract— Wireless topology control is the process of structuring the connectivity between network nodes to achieve some network-wide goal. This paper presents a cognitive networ...
Ryan W. Thomas, Ramakant S. Komali, Allen B. MacKe...
119
Voted
ATS
2003
IEEE
105views Hardware» more  ATS 2003»
15 years 9 months ago
Minimizing Defective Part Level Using a Linear Programming-Based Optimal Test Selection Method
Recent probabilistic test generation approaches have proven that detecting single stuck-at faults multiple times is effective at reducing the defective part level (DPL). Unfortuna...
Yuxin Tian, Michael R. Grimaila, Weiping Shi, M. R...
132
Voted
IJAIT
2007
119views more  IJAIT 2007»
15 years 3 months ago
Minimizing the makespan for Unrelated Parallel Machines
In this paper, we study the unrelated parallel machine problem for minimizing the makespan, which is NP-hard. We used Simulated Annealing (SA) and Tabu Search (TS) with Neighborho...
Yunsong Guo, Andrew Lim, Brian Rodrigues, Liang Ya...
121
Voted
DAC
2007
ACM
16 years 4 months ago
Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization
Power gating is one of the most effective ways to reduce leakage power. In this paper, we introduce a new relationship among Maximum Instantaneous Current, IR drops and sleep tran...
De-Shiuan Chiou, Da-Cheng Juan, Yu-Ting Chen, Shih...
146
Voted
ICCAD
2004
IEEE
150views Hardware» more  ICCAD 2004»
16 years 17 days ago
Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth
— This paper presents Hermes, a depth-optimal LUT based FPGA mapping algorithm. The presented algorithm is based on a new strategy for finding LUTs allowing to find a good LUT ...
Maxim Teslenko, Elena Dubrova