1008 search results - page 97 / 202 » Minimizing Average Flow-Time |
DATE
2004
IEEE
15 years 4 months ago
2004
IEEE
Tile-based data layout has been applied to achieve various objectives such as minimizing cache conflicts and memory row switching activity. In some applications of tilebased mappi...
85
Voted
ICS
2000
Tsinghua U.
15 years 4 months ago
2000
Tsinghua U.
One of the main concerns in today's processor design is the issue logic. Instruction-level parallelism is usually favored by an out-of-order issue mechanism where instruction...
118
Voted
ASPDAC
1995
ACM
15 years 4 months ago
1995
ACM
— The goal of transistor reordering for a logic gate is to reduce the propagation delay as well as the charging and discharging of internal capacitances to achieve low power cons...
EUROPAR
1997
Springer
15 years 4 months ago
1997
Springer
Abstract. The serialization constraints induced by the detection and enforcement of true data dependences have always been regarded as requirements for correct execution. We propos...
ICCAD
1995
IEEE
15 years 4 months ago
1995
IEEE
Pad assignment with signal integrity optimization is very important for high-speed VLSI design. In this paper, an efficient method is proposed to effectively minimize both simulta...