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» Minimizing Congestion in General Networks
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ICCAD
1994
IEEE
131views Hardware» more  ICCAD 1994»
15 years 1 months ago
Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
Hannah Honghua Yang, D. F. Wong
GIS
2007
ACM
15 years 10 months ago
Evacuation route planning: scalable heuristics
Given a transportation network, a vulnerable population, and a set of destinations, evacuation route planning identifies routes to minimize the time to evacuate the vulnerable pop...
Sangho Kim, Betsy George, Shashi Shekhar
PODC
2009
ACM
15 years 10 months ago
Tight bounds for clock synchronization
d Abstract] Christoph Lenzen Computer Engineering and Networks Laboratory (TIK) ETH Zurich, 8092 Zurich, Switzerland lenzen@tik.ee.ethz.ch Thomas Locher Computer Engineering and N...
Christoph Lenzen, Thomas Locher, Roger Wattenhofer
MOBISYS
2008
ACM
15 years 9 months ago
Composcan: adaptive scanning for efficient concurrent communications and positioning with 802.11
Using 802.11 concurrently for communications and positioning is problematic, especially if location-based services (e.g., indoor navigation) are concurrently executed with real-ti...
Mikkel Baun Kjærgaard, Thomas King
MOBICOM
2006
ACM
15 years 3 months ago
Cooperative collision warning using dedicated short range wireless communications
The emergence of the 802.11a-based Dedicated Short Range Communications (DSRC) standard and advances in mobile ad hoc networking create ample opportunity for supporting delay-crit...
Tamer A. ElBatt, Siddhartha K. Goel, Gavin Holland...