4 search results - page 1 / 1 » Mismatch Effects in Time-Interleaved Oversampling Converters |
ISCAS
1994
IEEE
13 years 10 months ago
1994
IEEE
WCNC
2010
IEEE
13 years 10 months ago
2010
IEEE
Abstract—Realization of all-digital baseband receiver processing for multi-Gigabit communication requires analog-to-digital converters(ADCs) of sufficient rate and output resolu...
ISCAS
2007
IEEE
14 years 17 days ago
2007
IEEE
— Mismatches between sample-and-hold (S/H) circuits in a time-interleaved analog-to-digital data converter (ADC) cause undesirable distortions in the output spectrum. To reduce t...
ISCAS
2005
IEEE
13 years 12 months ago
2005
IEEE
This paper presents novel low-voltage high order single loop sigma-delta modulator structures for wideband applications. The proposed architectures employ the technique of double-...