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IEEEPACT
2006
IEEE
16 years 13 days ago
Whole-program optimization of global variable layout
On machines with high-performance processors, the memory system continues to be a performance bottleneck. Compilers insert prefetch operations and reorder data accesses to improve...
Nathaniel McIntosh, Sandya Mannarswamy, Robert Hun...
IEEEPACT
2006
IEEE
16 years 13 days ago
Region array SSA
Static Single Assignment (SSA) has become the intermediate program representation of choice in most modern compilers because it enables efficient data flow analysis of scalars an...
Silvius Rus, Guobin He, Christophe Alias, Lawrence...
IEEEPACT
2006
IEEE
16 years 13 days ago
Branch predictor guided instruction decoding
Fast instruction decoding is a challenge for the design of CISC microprocessors. A well-known solution to overcome this problem is using a trace cache. It stores and fetches alrea...
Oliverio J. Santana, Ayose Falcón, Alex Ram...
IEEEPACT
2006
IEEE
16 years 13 days ago
Adaptive reorder buffers for SMT processors
In SMT processors, the complex interplay between private and shared datapath resources needs to be considered in order to realize the full performance potential. In this paper, we...
Joseph J. Sharkey, Deniz Balkan, Dmitry Ponomarev
IROS
2006
IEEE
136views Robotics» more  IROS 2006»
16 years 13 days ago
Adaptive Interacting Multiple Models applied on pedestrian tracking in car parks
— To address perception problems we must be able to track dynamics targets of the environment. An important issue of tracking is filtering problem in which estimates of the targ...
Julien Burlet, Olivier Aycard, Anne Spalanzani, Ch...
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