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ERSA
2007
177views Hardware» more  ERSA 2007»
14 years 11 months ago
Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors
- Even though state-of-the-art FPGAs present new opportunities in exploring low-cost high-performance architectures for floating-point scientific applications, they also pose serio...
Xiaofang Wang, Sotirios G. Ziavras, Jie Hu
EMNLP
2008
14 years 11 months ago
Online Large-Margin Training of Syntactic and Structural Translation Features
Minimum-error-rate training (MERT) is a bottleneck for current development in statistical machine translation because it is limited in the number of weights it can reliably optimi...
David Chiang, Yuval Marton, Philip Resnik
NIPS
2008
14 years 11 months ago
Asynchronous Distributed Learning of Topic Models
Distributed learning is a problem of fundamental interest in machine learning and cognitive science. In this paper, we present asynchronous distributed learning algorithms for two...
Arthur Asuncion, Padhraic Smyth, Max Welling
MASCOTS
2007
14 years 11 months ago
A Novel Flow Control Scheme for Best Effort Traffic in NoC Based on Source Rate Utility Maximization
—Advances in semiconductor technology, has enabled designers to put complex, massively parallel multiprocessor systems on a single chip. Network on Chip (NoC) that supports high ...
Mohammad Sadegh Talebi, Fahimeh Jafari, Ahmad Khon...
SODA
2008
ACM
80views Algorithms» more  SODA 2008»
14 years 11 months ago
Provably good multicore cache performance for divide-and-conquer algorithms
This paper presents a multicore-cache model that reflects the reality that multicore processors have both per-processor private (L1) caches and a large shared (L2) cache on chip. ...
Guy E. Blelloch, Rezaul Alam Chowdhury, Phillip B....
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