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IPPS
2000
IEEE
15 years 9 months ago
Three Dimensional VLSI-Scale Interconnects
As processor speeds rapidly approach the Giga-Hertz regime, the disparity between process time and memory access time plays an increasing role in the overall limitation of processo...
Dennis W. Prather
ICS
2010
Tsinghua U.
15 years 7 months ago
The auction: optimizing banks usage in Non-Uniform Cache Architectures
The growing influence of wire delay in cache design has meant that access latencies to last-level cache banks are no longer constant. Non-Uniform Cache Architectures (NUCAs) have ...
Javier Lira, Carlos Molina, Antonio Gonzále...
IEEEPACT
1999
IEEE
15 years 9 months ago
On Reducing False Sharing while Improving Locality on Shared Memory Multiprocessors
The performance of applications on large shared-memory multiprocessors with coherent caches depends on the interaction between the granularity of data sharing, the size of the coh...
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanuja...
ISHPC
1999
Springer
15 years 9 months ago
Utilization of Cache Area in On-Chip Multiprocessor
On-chip multiprocessor can be an alternative to the wide-issue superscalar processor approach which is currently the mainstream to exploit the increasing number of transistors on ...
Hitoshi Oi, N. Ranganathan
EUROPAR
2000
Springer
15 years 8 months ago
Design and Evaluation of a Compiler-Directed Collective I/O Technique
Abstract. Current approaches to parallel I/O demand extensive user effort to obtain acceptable performance. This is in part due to difficulties in understanding the characteristics...
Gokhan Memik, Mahmut T. Kandemir, Alok N. Choudhar...