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CONCUR
2007
Springer
15 years 7 months ago
Equivalence Checking for Infinite Systems Using Parameterized Boolean Equation Systems
Abstract. In this paper, we provide a transformation from the branching bisimulation problem for infinite, concurrent, data-intensive systems in linear process format, into solving...
Taolue Chen, Bas Ploeger, Jaco van de Pol, Tim A. ...
134
Voted
DSD
2010
IEEE
140views Hardware» more  DSD 2010»
15 years 3 months ago
RobuCheck: A Robustness Checker for Digital Circuits
Abstract—Continuously shrinking feature sizes cause an increasing vulnerability of digital circuits. Manufacturing failures and transient faults may tamper the functionality. Aut...
Stefan Frehse, Görschwin Fey, André S&...
71
Voted
DATE
2009
IEEE
79views Hardware» more  DATE 2009»
15 years 10 months ago
Solver technology for system-level to RTL equivalence checking
—Checking the equivalence of a system-level model against an RTL design is a major challenge. The reason is that usually the system-level model is written by a system architect, ...
Alfred Kölbl, Reily Jacoby, Himanshu Jain, Ca...
126
Voted
SPIN
2009
Springer
15 years 10 months ago
Improving Non-Progress Cycle Checks
This paper introduces a new model checking algorithm that searches for non-progress cycles, used mainly to check for livelocks. The algorithm performs an incremental depth-first s...
David Faragó, Peter H. Schmitt
117
Voted
FMICS
2007
Springer
15 years 10 months ago
Machine Checked Formal Proof of a Scheduling Protocol for Smartcard Personalization
Using PVS (Prototype Verification System), we prove that an industry designed scheduler for a smartcard personalization machine is safe and optimal. This scheduler has previously ...
Leonard Lensink, Sjaak Smetsers, Marko C. J. D. va...