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DATE
2004
IEEE
174views Hardware» more  DATE 2004»
15 years 7 months ago
Graph-Based Functional Test Program Generation for Pipelined Processors
Functional verification is widely acknowledged as a major bottleneck in microprocessor design. While early work on specification driven functional test program generation has prop...
Prabhat Mishra, Nikil Dutt
162
Voted
DDECS
2006
IEEE
146views Hardware» more  DDECS 2006»
15 years 7 months ago
Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis
Abstract-- Hard real-time systems need methods to determine upper bounds for their execution times, usually called worst-case execution times. Timing anomalies are counterintuitive...
Jochen Eisinger, Ilia Polian, Bernd Becker, Alexan...
145
Voted
FMCAD
2000
Springer
15 years 7 months ago
A Methodology for Large-Scale Hardware Verification
Abstract. We present a formal verification methodology for datapathdominated hardware. This provides a systematic but flexible framework within which to organize the activities und...
Mark Aagaard, Robert B. Jones, Thomas F. Melham, J...
WISES
2003
15 years 5 months ago
Automatic Recovery of the TTP/A Sensor/Actuator Network
Abstract — Since sensor/actuator networks are to be used in error-prone environments, it is required that media access protocols for such networks are tolerant to failures. Field...
Wilfried Steiner, Wilfried Elmenreich
GISCIENCE
2008
Springer
115views GIS» more  GISCIENCE 2008»
15 years 4 months ago
Validation and Storage of Polyhedra through Constrained Delaunay Tetrahedralization
Abstract. Closed, watertight, 3D geometries are represented by polyhedra. Current data models define these polyhedra basically as a set of polygons, leaving the test on intersectin...
Edward Verbree, Hang Si