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DAC
2002
ACM
16 years 5 months ago
A comparison of three verification techniques: directed testing, pseudo-random testing and property checking
This paper describes the verification of two versions of a bridge between two on-chip buses. The verification was performed just as the Infineon Technologies Design Centre in Bris...
Mike Bartley, Darren Galpin, Tim Blackmore
DSD
2009
IEEE
111views Hardware» more  DSD 2009»
15 years 11 months ago
Robustness Check for Multiple Faults Using Formal Techniques
Feature sizes in VLSI circuits are steadily shrinking. This results in increasing susceptibility to soft errors, e.g. due to environmental radiation. Precautions against soft error...
Stefan Frehse, Görschwin Fey, André S&...
150
Voted
EDBTW
2006
Springer
15 years 6 months ago
Efficient Integrity Checking over XML Documents
The need for incremental constraint maintenance within collections of semi-structured documents has been ever increasing in the last years due to the widespread diffusion of XML. T...
Daniele Braga, Alessandro Campi, Davide Martinengh...
113
Voted
JUCS
2007
108views more  JUCS 2007»
15 years 4 months ago
Integrating Module Checking and Deduction in a Formal Proof for the Perlman Spanning Tree Protocol (STP)
: In the IEEE 802.1D standard for the Media Access Control layer (MAC layer) bridges, there is an STP (Spanning Tree Protocol) definition, based on the algorithm that was proposed...
Hossein Hojjat, Hootan Nakhost, Marjan Sirjani
ICASSP
2010
IEEE
14 years 11 months ago
Statistical hypothesis testing with time-frequency surrogates to check signal stationarity
An operational framework is developed for testing stationarity relatively to an observation scale. The proposed method makes use of a family of stationary surrogates for defining ...
Cédric Richard, André Ferrari, Hassa...